Evgeni Perelroyzen
A current trend in digital design-the integration of the MATLAB® components Simulink® and Stateflow® for model building, simulations, system testing, and fault detection-allows for better control over the design flow process and, ultimately, for better system results. Digital Integrated Circuits: Design-for-Test Using Simulink® and Stateflow® illustrates the construction of Simulink models for digital project test benches in certain design-for-test fields.The first two chapters of the book describe the major tools used for design-for-test. The author explains the process of Simulink model building, presents the main library blocks of Simulink, and examines the development of finite-state machine modeling using Stateflow diagrams. Subsequent chapters provide examples of Simulink modeling and simulation for the latest design-for-test fields, including combinational and sequential circuits, controllability, and observability; deterministic algorithms; digital circuit dynamics; timing verification; built-in self-test (BIST) architecture; scan cell operations; and functional and diagnostic testing. The book also discusses the automatic test pattern generation (ATPG) process, the logical determinant theory, and joint test action group (JTAG) interface models.Digital Integrated Circuits explores the possibilities of MATLAB's tools in the development of application-specific integrated circuit (ASIC) design systems. The book shows how to incorporate Simulink and Stateflow into the process of modern digital design.
Simulink®: Dynamic System Simulation for MATLAB®. Stateflow®: Creating Finite State Machine Models. Fault Modeling and Simulation. Testability Analysis Methods. The Automatic Test Pattern Generation (ATPG) Process. Timing Verification. System and Embedded Core Testing. Index.
This book shows how to incorporate Simulink® and Stateflow® into the process of modern digital design. It describes the tools and concepts for simulating interactions, testing systems, and detecting design faults-allowing for better results in the design flow process. The book covers fault modeling and simulation, VLSI testability analysis, the ATPG process, deterministic algorithms, timing verification, and system and embedded core testing. It begins by introducing the Simulink and Stateflow tools, followed by deillegalscriptions of test development and simulation processes. The author also provides examples of Simulink modeling and simulation for the latest design-for-test fields.
Illustrates the construction of Simulink models for digital project test benches in certain design-for-test fields. This book explains the process of Simulink model building, presents the main library blocks of Simulink, and examines the development of finite-state machine modeling using Stateflow diagrams.
Inhaltsverzeichnis
INTRODUCTION SIMULINK(R): DYNAMIC SYSTEM SIMULATION FOR MATLAB(R) Introduction Creating a Model Running a Simulation Analyzing Simulation Results Subsystems: Using Masks to Customize Blocks Reference Blocks Simulink Debugger STATEFLOW(R): CREATING FINITE STATE MACHINE MODELS Introduction Creating Charts Entering a Stateflow Diagram Defining Events and Data Defining Stateflow Interfaces Exploring and Searching Debugging FAULT MODELING AND SIMULATION Fault Modeling Fault Simulation TESTABILITY ANALYSIS METHODS Combinational Controllability and Observability Analysis Models Sequential Controllability and Observability Analysis Models THE AUTOMATIC TEST PATTERN GENERATION (ATPG) PROCESS ATPG Fundamentals Combinational Circuit ATPG (Current-Based ATPG Algorithms for Combinational Circuits) TIMING VERIFICATION Logical Determinant Theory Digital Circuit Dynamics Model Building for Timing Verification SYSTEM AND EMBEDDED CORE TESTING Introduction Scan Path Architectures and Techniques System and Embedded Core Testing INDEX References appear at the end of each chapter.
Klappentext
This book shows how to incorporate Simulink and Stateflow into the process of modern digital design. It describes the tools and concepts for simulating interactions, testing systems, and detecting design faults-allowing for better results in the design flow process. The book covers fault modeling and simulation, VLSI testability analysis, the ATPG process, deterministic algorithms, timing verification, and system and embedded core testing. It begins by introducing the Simulink and Stateflow tools, followed by deillegalscriptions of test development and simulation processes. The author also provides examples of Simulink modeling and simulation for the latest design-for-test fields.
