Detailed discussion of on-chip interconnect, including theory, design, modelling and evaluation
Extensive Figure-of-Merit analyses for NPN transistors, which results are used for the design of several high bit-rate circuits and oscillators
Analyzing the consequences of circuit operation at supply voltages above transistor breakdown voltages
Many practical circuit examples, demonstrating the interplay between technology, interconnect and circuit design
John Long is Professor at the TU Delft and he is an expert in the RF / Ultrawideband field
Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the `interconnect´) and circuit design.
Circuit and Interconnet Design for RF and High Bit-rate Applications covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are `first-time right´. A thorough analysis of the interplay between on-chip circuits and interconnects is presented, including practical examples in high bit-rate and RF applications. Optimum interconnect geometries for the distribution of RF signals are described, together with simple models for standard interconnect geometries that capture characteristic impedance and propagation delay across a broad frequency range. The analyses also covers single-ended and differential geometries, so that the designer can incorporate the effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part.
Preface. 1. The Challenge. 1.1 Interconnect. 1.2 Device Metrics. 1.3 Cross-Connect Switches. 1.4 Transistor Operation above BVCEO. 1.5 CML circuits, PRBS generator. 1.6 Oscillators. 1.7 Outline of the book. References. 2. Interconnect Modelling, Analysis and Design. 2.1 Introduction. 2.2 Transmission Line Theory. 2.3 When to Include Transmission Line Effects. 2.4 Secondary Effects. 2.5 Resistivity-Frequency Mode Chart for a Microstrip Line. 2.6 Preferred Transmission Line Configurations. 2.7 Applying the Skin Effect Formulas to a SiGeBiCMOS Process. 2.8 Models including Skin Effect. 2.9 Signal Transfer Across a Transmission Line. 2.10 Interconnect Test Structures. 2.11 Modelling and Considerations of Digital Interconnect. 2.12 Circuit and Interconnect Design Flow. 2.13 Conclusions and Outlook. References. 3. Device Metrics. 3.1 Introduction. 3.2 Miller Effects. 3.3 Definitions based on y-Parameters. 3.4 Approximate Formulas for the Device Metrics. 3.5 Optimising a Technology for FA. 3.6 Relationship Between FA, FT and FMAX. 3.7 Trends in Device Metrics. 3.8 Other Trends. 3.9 Bipolar versus RF-CMOS. 3.10 Conclusions and Outlook. References. 4. Cross-Connect Switch Design. 4.1 Introduction. 4.2 Switch Matrix Design. 4.3 Buffer Circuits. 4.4 Complete RF Signal Path. 4.5 Supply Decoupling. 4.6 Experimental Results. 4.7 Conclusions and Outlook. 5. Bias Circuits Tolerating Output Voltages above BVCEO. 5.1 Introduction. 5.2 Principle of Collector-Base Avalanche Current. 5.3 Analysis of Simple 2-Transistor Current Mirrors. 5.4 Analysis of Current Mirrors with Internal Buffer. 5.5 Avalanche Current Compensation. 5.6 Conclusions and Outlook. 6. Design of Synchronous High Speed CML Circuits. 6.1 Introduction. 6.2 PRBS Background. 6.3 InP Technology. 6.4 PRBS Generator Design. 6.5 Experimental Results. 6.6 Distributed Capacitive Loading Reviewed. 6.7 Conclusionsand Outlook. References. 7. Analysis and Design of High Frequency LC-VCOs. 7.1 Introduction. 7.2 Input Impedance of a Cross-Coupled Differential Pair. 7.3 Input Impedance of a Capacitively-Loaded Emitter Follower. 7.4 Combining Negative Resistance and Output Buffer Functions. 7.5 LC-VCO Operating at a Frequency Close to FCROSS. 7.6 LC-VCO Operating at a Frequency Above FCROSS. 7.7 I/Q Signal Generation. 7.8 Conclusions and Outlook. References. Glossary. Appendix A. Index.
Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the `interconnect´) and circuit design. Circuit and Interconnect Design for RF and High Bit-rate Applications covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are `first-time right´. A thorough analysis of the interplay between on-chip circuits and interconnects is presented, including practical examples in high bit-rate and RF applications. Optimum interconnect geometries for the distribution of RF signals are described, together with simple models for standard interconnect geometries that capture characteristic impedance and propagation delay across a broad frequency range. The analyses also cover single-ended and differential geometries, so that the designer can incorporate the effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part.
From the technology perspective, transistor performance and its relationship to design targets for high bit-rate and RF applications is extensively discussed. Traditional figures of merit, such as fT and fmax and their relevance to circuit design are discussed, and new figures of merit are introduced that are shown to be highly valuable for broadband circuit and oscillator design. In addition, an analysis of transistor operation at supply voltages above breakdown voltage BVCEO, is presented.
Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the 'interconnect') and circuit design.
Circuit and Interconnet Design for RF and High Bit-rate Applications covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are 'first-time right'. A thorough analysis of the interplay between on-chip circuits and interconnects is presented, including practical examples in high bit-rate and RF applications. Optimum interconnect geometries for the distribution of RF signals are described, together with simple models for standard interconnect geometries that capture characteristic impedance and propagation delay across a broad frequency range. The analyses also covers single-ended and differential geometries, so that the designer can incorporate the effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part.
The Challenge.- Interconnect Modelling, Analysis and Design.- Device Metrics.- Cross-Connect Switch Design.- Bias Circuits Tolerating Output Voltages Above BVCEO.- Design of Synchronous High-Speed CML Circuits, a PRBS Generator.- Analysis and Design of High-Frequency LC-VCOs.
Über den Autor
John Long is Professor at the TU Delft and he is an expert in the RF / Ultrawideband field
Inhaltsverzeichnis
Preface. 1. The Challenge. 1.1 Interconnect. 1.2 Device Metrics. 1.3 Cross-Connect Switches. 1.4 Transistor Operation above BVCEO. 1.5 CML circuits, PRBS generator. 1.6 Oscillators. 1.7 Outline of the book. References. 2. Interconnect Modelling, Analysis and Design. 2.1 Introduction. 2.2 Transmission Line Theory. 2.3 When to Include Transmission Line Effects. 2.4 Secondary Effects. 2.5 Resistivity-Frequency Mode Chart for a Microstrip Line. 2.6 Preferred Transmission Line Configurations. 2.7 Applying the Skin Effect Formulas to a SiGeBiCMOS Process. 2.8 Models including Skin Effect. 2.9 Signal Transfer Across a Transmission Line. 2.10 Interconnect Test Structures. 2.11 Modelling and Considerations of Digital Interconnect. 2.12 Circuit and Interconnect Design Flow. 2.13 Conclusions and Outlook. References. 3. Device Metrics. 3.1 Introduction. 3.2 Miller Effects. 3.3 Definitions based on y-Parameters. 3.4 Approximate Formulas for the Device Metrics. 3.5 Optimising a Technology for FA. 3.6 Relationship Between FA, FT and FMAX. 3.7 Trends in Device Metrics. 3.8 Other Trends. 3.9 Bipolar versus RF-CMOS. 3.10 Conclusions and Outlook. References. 4. Cross-Connect Switch Design. 4.1 Introduction. 4.2 Switch Matrix Design. 4.3 Buffer Circuits. 4.4 Complete RF Signal Path. 4.5 Supply Decoupling. 4.6 Experimental Results. 4.7 Conclusions and Outlook. 5. Bias Circuits Tolerating Output Voltages above BVCEO. 5.1 Introduction. 5.2 Principle of Collector-Base Avalanche Current. 5.3 Analysis of Simple 2-Transistor Current Mirrors. 5.4 Analysis of Current Mirrors with Internal Buffer. 5.5 Avalanche Current Compensation. 5.6 Conclusions and Outlook. 6. Design of Synchronous High Speed CML Circuits. 6.1 Introduction. 6.2 PRBS Background. 6.3 InP Technology. 6.4 PRBS Generator Design. 6.5 Experimental Results. 6.6 Distributed Capacitive Loading Reviewed. 6.7 Conclusionsand Outlook. References. 7. Analysis and Design of High Frequency LC-VCOs. 7.1 Introduction. 7.2 Input Impedance of a Cross-Coupled Differential Pair. 7.3 Input Impedance of a Capacitively-Loaded Emitter Follower. 7.4 Combining Negative Resistance and Output Buffer Functions. 7.5 LC-VCO Operating at a Frequency Close to FCROSS. 7.6 LC-VCO Operating at a Frequency Above FCROSS. 7.7 I/Q Signal Generation. 7.8 Conclusions and Outlook. References. Glossary. Appendix A. Index.
Detailed discussion of on-chip interconnect, including theory, design, modelling and evaluation
Extensive Figure-of-Merit analyses for NPN transistors, which results are used for the design of several high bit-rate circuits and oscillators
Analyzing the consequences of circuit operation at supply voltages above transistor breakdown voltages
Many practical circuit examples, demonstrating the interplay between technology, interconnect and circuit design
