General introduction to SoC platform design and ESL design methodologies
Comprehensive overview of the state-of-the-art research on ESL design
Latest update on SystemC Transaction Level Modeling and standardization
Transaction-level timing formalism for architectural modeling of complex SoC platforms
Practical application in the context of ESL simulation and analysis tools and SoC architecture design
Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.
|We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore´s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.
Foreword. Preface.
1. INTRODUCTION. 1.1 Organization of the Book Chapters.
2. EMBEDDED SOC APPLICATIONS. 2.1 Networking Domain. 2.2 Multimedia Domain. 2.3 Wireless Communications. 2.4 Application Trends. 2.5 First Order Application Partitioning.
3. CLASSIFICATION OF PLATFORM ELEMENTS. 3.1 Architecture Metrics. 3.2 Processing Elements. 3.3 On-Chip Communication. 3.4 Summary.
4. SYSTEM LEVEL DESIGN PRINCIPLES. 4.1 The Platform Based Design Paradigm. 4.2 Design Phases. 4.3 Abstraction Mechanisms. 4.4 Models of Computation. 4.5 Object versus Actor Oriented Design. 4.6 System Level Design Requirements.
5. RELATED WORK. 5.1 Traditional HW/SW Co-Design. 5.2 SystemC based Transaction Level Modeling. 5.3 Current Research on MP-SoC Design Methodologies. 5.4 Summary.
6. METHODOLOGY OVERVIEW. 6.1 Application Modeling. 6.2 Architecture Modeling. 6.3 Envisioned Design Flow. 6.4 MP-SoC Simulation Framework.
7. UNIFIED TIMING MODEL. 7.1 Tagged Signal Model Introduction. 7.2 Reactive Process Network. 7.3 Architecture Model. 7.4 Performance Metrics. 7.5 Summary.
8. MP-SOC SIMULATION FRAMEWORK. 8.1 The Generic Synchronization Protocol. 8.2 Generic VPU Model. 8.3 NoC Framework. 8.4 Tool Support. 8.5 Summary.
9. CASE STUDY. 9.1 IPv4 Forwarding with QoS Support. 9.2 Intel IXP2400 Reference NPU. 9.3 Custom IPv4 Platform. 9.4 Simulation Results.
10. SUMMARY.
Appendices. A The OSCI TLM Standard. B The OCPIP TL3 Channel. C The Architects View Framework.
List of Figures. List of Tables. References. Index.
From the reviews:
"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool ... . This book´s scope and range of pragmatic ideas make it valuable for a wide audience. ... When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area ... . It should resonate with students, researchers, and practical designers ... ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)
We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore's law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.
Foreword. Preface.- 1. Introduction.- 2. Embedded SOC Applications.- 3. Classification of Platform Elements.- 4. System Level Design Principles.- 5. Related Work.- 6. Methodology Overview.- 7. Unified Timing Model.- 8. MP-SOC Simulation Framework.- 9. Case Study.- 10. Summary.- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework.- List of Figures. List of Tables. References.- Index.
From the reviews:
"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool ... . This book's scope and range of pragmatic ideas make it valuable for a wide audience. ... When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area ... . It should resonate with students, researchers, and practical designers ... ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)
Inhaltsverzeichnis
Foreword. Preface.
1. INTRODUCTION. 1.1 Organization of the Book Chapters.
2. EMBEDDED SOC APPLICATIONS. 2.1 Networking Domain. 2.2 Multimedia Domain. 2.3 Wireless Communications. 2.4 Application Trends. 2.5 First Order Application Partitioning.
3. CLASSIFICATION OF PLATFORM ELEMENTS. 3.1 Architecture Metrics. 3.2 Processing Elements. 3.3 On-Chip Communication. 3.4 Summary.
4. SYSTEM LEVEL DESIGN PRINCIPLES. 4.1 The Platform Based Design Paradigm. 4.2 Design Phases. 4.3 Abstraction Mechanisms. 4.4 Models of Computation. 4.5 Object versus Actor Oriented Design. 4.6 System Level Design Requirements.
5. RELATED WORK. 5.1 Traditional HW/SW Co-Design. 5.2 SystemC based Transaction Level Modeling. 5.3 Current Research on MP-SoC Design Methodologies. 5.4 Summary.
6. METHODOLOGY OVERVIEW. 6.1 Application Modeling. 6.2 Architecture Modeling. 6.3 Envisioned Design Flow. 6.4 MP-SoC Simulation Framework.
7. UNIFIED TIMING MODEL. 7.1 Tagged Signal Model Introduction. 7.2 Reactive Process Network. 7.3 Architecture Model. 7.4 Performance Metrics. 7.5 Summary.
8. MP-SOC SIMULATION FRAMEWORK. 8.1 The Generic Synchronization Protocol. 8.2 Generic VPU Model. 8.3 NoC Framework. 8.4 Tool Support. 8.5 Summary.
9. CASE STUDY. 9.1 IPv4 Forwarding with QoS Support. 9.2 Intel IXP2400 Reference NPU. 9.3 Custom IPv4 Platform. 9.4 Simulation Results.
10. SUMMARY.
Appendices. A The OSCI TLM Standard. B The OCPIP TL3 Channel. C The Architects View Framework.
List of Figures. List of Tables. References. Index.
Klappentext
We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore¿s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.
General introduction to SoC platform design and ESL design methodologies
Comprehensive overview of the state-of-the-art research on ESL design
Latest update on SystemC Transaction Level Modeling and standardization
Transaction-level timing formalism for architectural modeling of complex SoC platforms
Practical application in the context of ESL simulation and analysis tools and SoC architecture design
