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Multithreaded support to IPC in parallel architectures
(Englisch)
Tiziano De Matteis

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Multithreaded support to IPC in parallel architectures

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Autor/Autorin: De Matteis Tiziano

I was born in Tricase (Lecce - Italy) on January 16, 1987. I have pursuit my Bachelor and Master Degree at the University of Pisa.Currently I'm a PhD student at the University of Pisa, working in the Parallel Architecture Group.
Multithreaded architectures are becoming commercially diffused, also on commodity PC. The work of this thesis aims at investigating a possible way of exploiting this technology in High Performance Computing for supporting interprocess communication (IPC) in shared memory architectures. The goal is to emulate the functionalities of a communication processor when it is not physically available by means of helper threads.

I was born in Tricase (Lecce - Italy) on January 16, 1987. I have pursuit my Bachelor and Master Degree at the University of Pisa.Currently I'm a PhD student at the University of Pisa, working in the Parallel Architecture Group.

Über den Autor

I was born in Tricase (Lecce - Italy) on January 16, 1987. I have pursuit my Bachelor and Master Degree at the University of Pisa.Currently I'm a PhD student at the University of Pisa, working in the Parallel Architecture Group.


Klappentext

Multithreaded architectures are becoming commercially diffused, also on commodity PC. The work of this thesis aims at investigating a possible way of exploiting this technology in High Performance Computing for supporting interprocess communication (IPC) in shared memory architectures. The goal is to emulate the functionalities of a communication processor when it is not physically available by means of helper threads.



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