Comprehensive state-of-the-art survey of design and validation of computer architectures Systematic coverage providing a clear vision of the problems and advanced techniques for their solution Seven chapters by eminent researchers presuppose only basic knowledge and lead to the forefront of research
This state-of-the-art survey gives a systematic presentation of recent advances in the design and validation of computer architectures. The book covers a comprehensive range of architecture design and validation methods, from computer aided high-level design of VLSI circuits and systems to layout and testable design, including the modeling and synthesis of behavior and dataflow, cell-based logic optimization, machine assisted verification, and virtual machine design.|This book grew out of material which was taught at the International Summer School on Architecture Design and Validation Methods, held June 23-July 5, 1997, on the Island of Lipari and directed to graduate students and young researchers. Since then the course notes have been completely elaborated and extended and additional chapters have been added so that this book offers a comprehensive presentation of the state of the art which leads the reader to the forefront of the current research in the area. The chapters, each of which was written by a group of eminent special ists in the field, are self-contained and can be read independently of each other. They cover the wide range of theoretical and practical methods which currently used for the specification, design, validation and verification of are hardware/software architectures. Synthesis methods are the subject of the first three chapters. The chapter on Modeling and Synthesis of Behavior, Control and Data Flow focusses on techniques above the register-transfer level. The chapter on Cell-Based Logic Optimizations concentrates on methods that interface logic design with phys ical design, in particular on techniques for cell-library binding, the back-end of logic synthesis. The chapter on A Design Flow for Performance Planning presents new paradigms for iteration-free synthesis where global wire plans for meeting timing constraints already appear at the conceptual design stage, even before fixing the functionality of the blocks in the plan.
Modeling and Synthesis of Behavior, Control and Data Flow.- 1 Introduction.- 2 Behavioral Synthesis.- 3 High-Level Control.- 4 Data Flow.- 5 Conclusion.- References.- Cell-based Logic Optimization.- 1 Introduction.- 2 Problem Formulation and Analysis.- 3 Algorithms for Library Binding.- 4 Boolean Matching.- 5 Generalized Matching.- 6 Conclusion.- References.- A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis.- 1 Introduction.- 2 Flow Components.- 3 Layout Synthesis.- 4 Placement Versus Floorplan Design.- 5 Global Wires.- 6 Wire Planning.- 7 Gate Sizing.- 8 Conclusions.- References.- Test and Testable Design.- 1 Introduction.- 2 Defect Analysis and Fault Modeling.- 3 External Testing.- 4 Self-Testable Systems-On-Chip.- References.- Machine Assisted Verification.- 1 Introduction.- 2 Logic Verification.- 3 Bit-Vector and Word-Level Verification.- 4 Verification by Fixed-Point Calculations.- 5 Verification Techniques for Bounded State Sequences.- 6 Formally Correct Construction of Pipelined Systems.- References.- Models of Computation for System Design.- 1 Introduction.- 2 MOCs: Basic Concepts and the Tagged Signal Model.- 3 Common Models of Computation.- 4 Codesign Finite State Machines.- 5 Conclusions.- References.- Modular Design for the Java Virtual Machine Architecture.- 1 Introduction.- 2 The Trustful Virtual Machine.- 3 The Defensive Virtual Machine.- 4 The Diligent Virtual Machine.- 5 The Dynamic Virtual Machine.- 6 Related and Future Work.- 7 The JVM Abstract State Machine.
This book grew out of material which was taught at the International Summer School on Architecture Design and Validation Methods, held June 23-July 5, 1997, on the Island of Lipari and directed to graduate students and young researchers. Since then the course notes have been completely elaborated and extended and additional chapters have been added so that this book offers a comprehensive presentation of the state of the art which leads the reader to the forefront of the current research in the area. The chapters, each of which was written by a group of eminent special ists in the field, are self-contained and can be read independently of each other. They cover the wide range of theoretical and practical methods which currently used for the specification, design, validation and verification of are hardware/software architectures. Synthesis methods are the subject of the first three chapters. The chapter on Modeling and Synthesis of Behavior, Control and Data Flow focusses on techniques above the register-transfer level. The chapter on Cell-Based Logic Optimizations concentrates on methods that interface logic design with phys ical design, in particular on techniques for cell-library binding, the back-end of logic synthesis. The chapter on A Design Flow for Performance Planning presents new paradigms for iteration-free synthesis where global wire plans for meeting timing constraints already appear at the conceptual design stage, even before fixing the functionality of the blocks in the plan.
Egon Börger ist Professor für Informatik an der Universität Pisa (Italien) und Alexander-von-Humboldt-Forschungspreisträger.
Inhaltsverzeichnis
Modeling and Synthesis of Behavior, Control and Data Flow.- 1 Introduction.- 2 Behavioral Synthesis.- 3 High-Level Control.- 4 Data Flow.- 5 Conclusion.- References.- Cell-based Logic Optimization.- 1 Introduction.- 2 Problem Formulation and Analysis.- 3 Algorithms for Library Binding.- 4 Boolean Matching.- 5 Generalized Matching.- 6 Conclusion.- References.- A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis.- 1 Introduction.- 2 Flow Components.- 3 Layout Synthesis.- 4 Placement Versus Floorplan Design.- 5 Global Wires.- 6 Wire Planning.- 7 Gate Sizing.- 8 Conclusions.- References.- Test and Testable Design.- 1 Introduction.- 2 Defect Analysis and Fault Modeling.- 3 External Testing.- 4 Self-Testable Systems-On-Chip.- References.- Machine Assisted Verification.- 1 Introduction.- 2 Logic Verification.- 3 Bit-Vector and Word-Level Verification.- 4 Verification by Fixed-Point Calculations.- 5 Verification Techniques for Bounded State Sequences.- 6 Formally Correct Construction of Pipelined Systems.- References.- Models of Computation for System Design.- 1 Introduction.- 2 MOCs: Basic Concepts and the Tagged Signal Model.- 3 Common Models of Computation.- 4 Codesign Finite State Machines.- 5 Conclusions.- References.- Modular Design for the Java Virtual Machine Architecture.- 1 Introduction.- 2 The Trustful Virtual Machine.- 3 The Defensive Virtual Machine.- 4 The Diligent Virtual Machine.- 5 The Dynamic Virtual Machine.- 6 Related and Future Work.- 7 The JVM Abstract State Machine.
Klappentext
This book grew out of material which was taught at the International Summer School on Architecture Design and Validation Methods, held June 23-July 5, 1997, on the Island of Lipari and directed to graduate students and young researchers. Since then the course notes have been completely elaborated and extended and additional chapters have been added so that this book offers a comprehensive presentation of the state of the art which leads the reader to the forefront of the current research in the area. The chapters, each of which was written by a group of eminent special ists in the field, are self-contained and can be read independently of each other. They cover the wide range of theoretical and practical methods which currently used for the specification, design, validation and verification of are hardware/software architectures. Synthesis methods are the subject of the first three chapters. The chapter on Modeling and Synthesis of Behavior, Control and Data Flow focusses on techniques above the register-transfer level. The chapter on Cell-Based Logic Optimizations concentrates on methods that interface logic design with phys ical design, in particular on techniques for cell-library binding, the back-end of logic synthesis. The chapter on A Design Flow for Performance Planning presents new paradigms for iteration-free synthesis where global wire plans for meeting timing constraints already appear at the conceptual design stage, even before fixing the functionality of the blocks in the plan.
Comprehensive state-of-the-art survey of design and validation of computer architectures Systematic coverage providing a clear vision of the problems and advanced techniques for their solution Seven chapters by eminent researchers presuppose only basic knowledge and lead to the forefront of research
Includes supplementary material: sn.pub/extras
