1 The Mechanisms of Hot Carrier Degradation.- 1.1 Introduction.- 1.2 Injection of Channel Hot Carriers in MOSFETs.- 1.3 Characterization Techniques.- 1.4 Charge Trapping and Dit-Generation Under Uniform Hot-Carrier Injection in MOSFETs.- 1.5 Charge Trapping and Dit-Generation Under Nonuniform Hot-Carrier Injection in MOSFETs.- 1.6 Conclusions.- 1.7 Acknowledgments.- References.- 2 Hot-Carrier Degradation Effects for DRAM Circuits.- 2.1 Introduction.- 2.2 Hot-Carrier Degradation in MOSFETs.- 2.3 Hot Carrier Impact on Circuit Operation.- 2.4 Circuit Hot-Electron Effect Simulation.- 2.5 ESD Latent Damage and Hot-Electron Reliability.- 2.6 Future Issues.- 2.7 Conclusions.- 2.8 Acknowledgments.- References.- 3 Hot Carrier Design Considerations in MOS Nonvolatile Memories.- 3.1 Introduction.- 3.2 Hot Carriers and EPROM.- 3.3 Hot Carriers and Flash Memory.- 3.4 Hot Carriers and Floating-Gate-Type EEPROMs.- 3.5 Hot Carriers and MNOS-Type EEPROMs.- 3.6 Conclusions.- 3.7 Acknowledgments.- References.- 4 Hot-Carrier Degradation During Dynamic Stress.- 4.1 The Problem of AC Hot-Carrier Degradation.- 4.2 Discussion of Transient Effects.- 4.3 Dynamic Degradation in Circuits.- 4.4 Conclusions.- References.- Appendices.- Appendix I On the Mathematical Formalism of the Hot-Carrier Currents in Semiconductor DevicesCheng T. Wang.- A1.1 Introduction.- A1.2 Mathematical Formalism.- A1.3 Conclusion.- References.- Appendix II Non-Local Field Effects on Carrier Transport in Ultra-Small-Size Devices Cheng T. Wang.- A2.1 Introduction.- A2.3 Drift Velocity as a Function of Distance.- A2.4 A Comparative Study of Field Effect on Drift Velocity.- A2.5 Conclusion.- A2.6 Acknowledgments.- References.
As device dimensions decrease, hot-carrier effects, which are due mainly to the presence of a high electric field inside the device, are becoming a major design concern. On the one hand, the detrimental effects-such as transconductance degradation and threshold shift-need to be minimized or, if possible, avoided altogether. On the other hand, performance such as the programming efficiency of nonvolatile memories or the carrier velocity inside the devices-need to be maintained or improved through the use of submicron technologies, even in the presence of a reduced power supply. As a result, one of the major challenges facing MOS design engineers today is to harness the hot-carrier effects so that, without sacrificing product performance, degradation can be kept to a minimum and a reli able design obtained. To accomplish this, the physical mechanisms re sponsible for the degradations should first be experimentally identified and characterized. With adequate models thus obtained, steps can be taken to optimize the design, so that an adequate level of quality assur ance in device or circuit performance can be achieved. This book ad dresses these hot-carrier design issues for MOS devices and circuits, and is used primarily as a professional guide for process development engi neers, device engineers, and circuit designers who are interested in the latest developments in hot-carrier degradation modeling and hot-carrier reliability design techniques. It may also be considered as a reference book for graduate students who have some research interests in this excit ing, yet sometime controversial, field.
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