1 Yield Models for Defect-Tolerant VLSI Circuits: A Review.- 2 Wafer Scale Revisited.- 3 Models for Defects and Yield.- Defects, Faults and Semiconductor Device Yield.- On the Probability of Fault Occurrence.- A New Yield Formula for Fault-Tolerant Large Area Devices.- 4 Defect-Tolerant Designs.- Defect Tolerant Interconnects for VLSI.- Combining Architecture and Algorithm for Yield Enhancement and Fault Tolerance.- Design of a Fault-Tolerant DRAM with New On-Chip ECC.- 5 Defect Monitoring and Yield Projection.- Measurement and Distribution of Faults on Defect Test Site Chips.- Process Development and Circuit Design Interactions in VLSI Yield Improvement.- Yield Projection Based on Electrical Fault Distribution and Critical Structure Analysis.- Yield Model for Yield Projection from Test Site.- 6 Testing and Testable Designs.- Test Methods for Wafer-Scale Integration.- Fault Diagnosis of Linear Processor Arrays.- Fault Diagnosis of Array Processors with Uniformly Distributed Faults.- 7 Defect- and Fault-Tolerant Processors.- Designing for High Yield: The NS32532 Microprocessor.- Defect Tolerance in a 16 Bit Microprocessor.- Design Techniques for a Self-Checking Self-Exercising Processor.- Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.- 8 Defect- and Fault-Tolerant Memories.- Diagnosis and Repair of Large Memories: A Critical Review and Recent Results.- A Reconfigurable SRAM 4.5 MBit WSI Memory.- Block Alignment: A Method for Increasing the Yield of Memory Chips that are Partially Good.- Fault Tolerant Integrated Memory Design.- 9 Reconfigurable Arrays.- Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays.- Fabrication-Time and Run-Time Fault-Tolerant Array Processors Using Single-Track Switches.- An Efficient Restructuring Approach for Wafer Scale Processor Arrays.- Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-Dimensional Arrays.- A General Model for Fault Covering Problems in Reconfigurable Arrays.- 10 Fault-Tolerant Arrays.- Defect Tolerance in a Wafer Scale Array for Image Processing.- Distributed Fault-Tolerant Embedding of Binary Trees and Rings in Hypercubes.- On the Analysis and Design of Hierarchical Fault-Tolerant Processor Arrays.- Contributors.
This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.
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