Introduction.- Conventional Architecture of Turbo Decoder.- Turbo Decoder with Parallel Processing.- Low-Complexity Solution for Highly Parallel Architecture.- High Efficiency Solution for Highly Parallel Architecture.
This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.
Offers readers a complete introduction to practical turbo decoder design
Describes different design methodologies and explains the trade-offs between performance improvement and overhead
Explains modern techniques for state-of-the-art designs
Includes simulation and implementation results with respect to various decoder circuit designs
Reveals novel approaches to higher operating efficiency of turbo decoders for beyond 4G applications