Introduction; Related work; Background; Statistical Regression Based Power Models; Statistical Regression Based Power Models for FPGAs; High Level Simulation Directed RTL Power Estimation; Applying Verification Collaterals for Accurate Power Estimation; Architectural Selection using High Level Synthesis; Power Reduction using High-Level Clock-gating; Model-Checking to exploit Sequential Clock-Gating; Power model to facilitate aggressive reduction; Coprocessor Design Space Exploration using High Level Synthesis.
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
Integrates power estimation and reduction for high level synthesis, with low-power, high-level design
Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives
Covers techniques from RTL/gate-level to hardware software co-design