Preface. 1. Introduction. 2. Methods for Nominal Analog Circuit Synthesis. 3. A New Nominal Synthesis Strategy. 4. Synthesis Via Annealing. 5. A Circuit Compiler. 6. Nominal Circuit Synthesis Results. 7. Validating the Tool Design. 8. The Second Challenge: Handling Variations. 9. A Unified Formulation. 10. Solving the Infinite Program. 11. Variation-Tolerant Synthesis Results. 12. Conclusions and Future Work. Bibliography. Index.
Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits.
Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise.
But the world is not solely digital.
Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market.
Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluatio
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