It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a deillegalscriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
Foreword. Preface. 0. Giving Semantics to VHDL: an Introduction; C. Delgado Kloos, P.T. Breuer. 1. A Functional Semantics for Delta-Delay VHDL Based on Focus; M. Fuchs, M. Mendler. 2. A Functional Semantics for Unit-Delay VHDL; P.T. Breuer, L. Sánchez Fernanández, C. Delgado Kloos. 3. An Operational Semantics for a Subset of VHDL; J.P. Van Tassel. 4. A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines; E. Börger, U. Glässer, W. Müller. 5. A Formal Model of VHDL Using Coloured Petri Nets; S. Olcoz. 6. A Deterministic Finite-State Model for VHDL; G. Döhmen, R. Herrmann. 7. A Flow Graph Semantics of VHDL: a Basis for Hardware Verification with VHDL; R. Reetz, T. Kropf. References.
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a deillegalscriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
0 Giving Semantics to VHDL: An Introduction.- 1 VHDL.- 2 Semantics.- 3 A Running Example.- 4 Contents of this book.- 1 A Functional Semantics for Delta-Delay VHDL Based on Focus.- 1 Introduction.- 2 A Motivating Example.- 3 Assumptions.- 4 Formal Semantics for ?-VHDL.- 5 Conclusion.- Appendix A Syntax of ?-VHDL.- 2 A Functional Semantics for Unit-Delay VHDL.- 1 Introduction.- 2 The VHDL Subset.- 3 Functional Semantics.- 4 Summary and Future Work.- Appendix A Auxiliary Function Definitions.- 3 An Operational Semantics for a Subset of VHDL.- 1 Introduction.- 2 Related Research.- 3 Syntax.- 4 Operational Semantics.- 5 Information Organization.- 6 Rules of the Semantics.- 7 Equivalence.- 8 A NAND Gate.- 9 Conclusions.- 4 A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines.- 1 Introduction.- 2 Related Work.- 3 EA-Machines.- 4 The Formal Model.- 5 Example.- 6 Conclusion & Future Directions.- Appendix A Elaborated Example.- 5 A Formal Model of VHDL Using Coloured Petri Nets.- 1 Introduction.- 2 VHDL Event-Driven Simulation.- 3 The VHDL Execution Model.- 4 Variables, Types and Expressions.- 5 Statements, Subprograms and Processes.- 6 Implementation of a CPN Model Generator.- 7 Conclusions.- 6 A Deterministic Finite-State Model for VHDL.- 1 Introduction.- 2 Generation of the Finite-State Model.- 3 Conclusion.- Appendix A Elaborated Running Example.- Appendix B Utility Functions.- 7 A Flow Graph Semantics of VHDL: A Basis for Hardware Verification with VHDL.- 1 Introduction.- 2 Flow Graph Model.- 3 Semantics of VHDL.- 4 The Example.- 5 Verification.- 6 Conclusion and Future Work.- References.
Inhaltsverzeichnis
Foreword. Preface. 0. Giving Semantics to VHDL: an Introduction; C. Delgado Kloos, P.T. Breuer. 1. A Functional Semantics for Delta-Delay VHDL Based on Focus; M. Fuchs, M. Mendler. 2. A Functional Semantics for Unit-Delay VHDL; P.T. Breuer, L. Sánchez Fernanández, C. Delgado Kloos. 3. An Operational Semantics for a Subset of VHDL; J.P. Van Tassel. 4. A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines; E. Börger, U. Glässer, W. Müller. 5. A Formal Model of VHDL Using Coloured Petri Nets; S. Olcoz. 6. A Deterministic Finite-State Model for VHDL; G. Döhmen, R. Herrmann. 7. A Flow Graph Semantics of VHDL: a Basis for Hardware Verification with VHDL; R. Reetz, T. Kropf. References.
Klappentext
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a deillegalscriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
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