* Introduction * Coherence, synchronization, and allocation * Power-aware, reliable, and reconfigurable memory * Software-based memory tuning * Architecture-based tuning * Workload considerations * Index
The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap.
Edited by leading international authorities in the field, this new
work provides a survey from researchers and practitioners on advances
in technology, architecture, and algorithms that address scalability
needs in multiprocessors and the expanding gap between CPU/network and
memory speeds. It is ideally suited to researchers and R & D
professionals with interests or practice in computer engineering,
computer architecture, and processor architecture.