Introduction.- Constrained Random Simulation.- High Level Verification Languages.- Assertion Languages and Constraints.- Preliminaries.- Constrained Vector Generation.- Constraint Simplification.- More Optimizations.- Constraint Synthesis.- Constraint Diagnosis.- Word-Level Constraint Solving.-
Covers the methodology and state-of-the-art techniques of constrained verification, which is new and popular.
It relates constrained verification with the also-hot technology called assertion-based design.
Discussed and clarifies language issues, critical to both the above, which will help the implementation of these languages.
As the complexity and miniaturization of electronic hardware advances, more time and money is actually now spent on testing and verification than in the preliminary design stage. This practical-oriented guidebook covers both the fundamentals and the techniques of constraint-based testbench automation. The book compares and contrasts constraint-based verification with traditional testbench approaches: test generation (a key concept), simulation monitoring, and coverage. Related aspects of verification languages such as e/vera/PSL/OVL/SVA are also covered. On the technical side, state-of-the art algorithms of test generation, performance optimization, and randomization are explained.