to Video Coding and H.264/AVC.- Intra Prediction.- Integer Motion Estimation.- Fractional Motion Estimation.- Motion Compensation.- Transform Coding.- Deblocking Filter.- CABAC Encoder.- System Integration.
High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.
This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.
Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding
Employs massively parallel processing to deliver up to 33 million pixels, with efficient design that can be prototyped via FPGA
Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification
Verilog RTL codes and testbenches available for download