Present a dynamic and reconfigurable architecture for future wireless communication systems, e.g. 5G and beyond
Introduces massive multiple-input multiple-output (MIMO) technology, which can improve network capacity, enhance network robustness and reduce communication delays
Reviews various implementations of the architecture and explains the ASIC-based approach, which offers high energy efficiency, high area efficiency and low detection error
Professor Leibo Liu received his bachelor's and doctoral degrees in Electronic Engineering and Microelectronics from Tsinghua University in 1999 and 2004, respectively. He subsequently taught at the European Microelectronics Center, Massachusetts Institute of Technology, and the University of Oxford (in 2006, 2013 and 2017). He is currently a Tsinghua Microelectronics Director (Tenured Professor). He has long been engaged in reconfigurable computing and has supervised more than 10 projects including key projects of the 863 Program (Chief Expert), National Natural Science Foundation, Basic Research Project of the National Defense Science and Technology Bureau, and major international cooperation projects. He has published more than 80 SCI-indexed papers and more than 60 EI-indexed papers.
In the course of his career, he has won e.g. the National Technology Invention Award (second prize), the China Patent Gold Award, the Ministry of Education Technology Invention Award (first prize), and the Jiangxi Science and Technology Progress Award (second prize).
This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error.
After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.
CHAPTER 1 INTRODUCTION ............................................................................................................................................. 4
1.1. Application Requirements .................................................................................................................................... 5
1.1.1 Typical Applications in Future ..........................................................................................................................................5
1.1.2 Communication System Requirements .............................................................................................................................8
1.2 Mobile Communication and MIMO Detection ................................................................................................... 11
1.2.1 Development of Communication Technologies ..............................................................................................................11
1.2.2 Key 5G Technologies ......................................................................................................................................................12
1.2.3 MIMI Baseband Processing ............................................................................................................................................17
1.2.4 Difficulties in Massive MIMO Detection .......................................................................................................................22
1.3 Status Quo of MIMO Detection Chip Research .................................................................................................. 23
1.3.1 ISAP-based MIMO Detection Chip ................................................................................................................................23
1.3.2 ASIC-based MIMO Detection Chip ................................................................................................................................29
1.3.3 Limitation of Traditional MIMO Detection Chips ..........................................................................................................43
1.4 Dynamic Reconfigurable Chip Technologies of MIMO Detection ..................................................................... 44
1.4.1 Overview of Reconfigurable Computing ........................................................................................................................44
1.4.2 Status Quo of Dynamic Reconfiguration Chip of MIMO Detection ...............................................................................52
CHAPTER 2 LINEAR MASSIVE MIMO DETECTION ALGORITHM .................................................................................... 68
2.1 Analysis of Linear Detection Algorithm .............................................................................................................. 68
2.2 Neumann Series Approximation Algorithm ........................................................................................................ 71
2.2.1 Algorithm Design ........................................................................................................................................................71
2.2.2 Error Analysis ..............................................................................................................................................................72
2.2.3 Complexity and Block Error Rate ...................................................................................................................................75
2.3 Chebyshev Iteration Algorithm ........................................................................................................................... 79
2.3.1 Algorithm Design ............................................................................................................................................................79
2.3.2 Convergence ...................................................................................................................................................................83
2.3.3 Complexity and Parallelism ............................................................................................................................................87
2.3.4 Bit Error Rate ..................................................................................................................................................................89
2.3.5 Analysis on Channel Model Impact ................................................................................................................................93
2.4 Jacobi Iteration Algorithm .................................................................................................................................. 95
2.4.1 Weighted Jacobi Iteration and Convergence ...................................................................................................................95
2.4.2 Complexity and Frame Error Rate ..................................................................................................................................99
2.4.3 Analyses on Channel Model Effects .............................................................................................................................103
2.5 Conjugate Gradient Algorithm ......................................................................................................................... 104
2.5.1 Algorithm Design ..........................................................................................................................................................104
2.5.2 Convergence ..............................................................................................................................................................106
2.5.3 Initial Iteration Value and Search ..................................................................................................................................107
2.5.4 Complexity and Parallelism ..........................................................................................................................................111
2.5.5 Symbol Error Rate ........................................................................................................................................................112
CHAPTER 3 ARCHITECTURE OF LINEAR MASSIVE MIMO DETECTION ........................................................................ 117
3.1 NSA-based Hardware Architecture ................................................................................................................... 117
3.1.1 VLSI Top-level Structure ..............................................................................................................................................117
3.1.2 Approximate Inversion and Matched Filtering Module ................................................................................................118
3.1.3 Equalization and SINR Module ....................................................................................................................................119
3.1.4 IFFT and LLR Module..................................................................................................................................................120
3.1.5 Inverse Module Based on Cholesky Decomposition ....................................................................................................120
3.2 Chebyshev Iteration Hardware Architecture .................................................................................................... 122
3.2.1 VLSI Top-level Structure ..............................................................................................................................................122
3.2.2 Initial Module ...............................................................................................................................................................123
3.2.3 Iterative Module ............................................................................................................................................................124
3.2.4 LLR Module .................................................................................................................................................................125
3.2.5 Experimental Results and Comparison .........................................................................................................................126
3.3 Hardware Architecture Based on Weighted Jacobi Iteration ......................................................................... 129
3.3.1 VLSI Top-level Architecture .........................................................................................................................................129
3.3.2 Diagonal Systolic Array ................................................................................................................................................130
3.3.3 WeJi Module .................................................................................................................................................................132
3.3.4 LLR Module .................................................................................................................................................................135
3.3.5 Experimental Result and Comparison ...........................................................................................................................135
3.4 Hardware Architecture Based on Conjugate Gradient Method ........................................................................ 141
3.4.1 VLSI Top-level Structure ..............................................................................................................................................141
3.4.2 Input/Output Module ....................................................................................................................................................141
3.4.3 Multiplication Module ..................................................................................................................................................142
3.4.4 Iterative Module ............................................................................................................................................................144
3.4.5 Experimental Results and Comparison .........................................................................................................................145
CHAPTER 4 NONLINEAR MASSIVE MIMO SIGNAL DETECTION ALGORITHM ............................................................... 150
4.1 conventional Nonlinear MIMO Signal Detection Algorithm ............................................................................. 150
4.1.1 ML Signal Detection Algorithm .....................................................................................................................................150
4.1.2 SD Signal Detection Algorithm and K-Best Signal Detection Algorithm ........................................................................152
4.2 CHOSLAR Algorithm .......................................................................................................................................... 156
4.2.1 System Model ...............................................................................................................................................................156
4.2.2 QR Decomposition ........................................................................................................................................................156
4.2.3 Lattice Reduction ..........................................................................................................................................................158
4.2.4 Cholesky Pre-processing ...............................................................................................................................................159
4.2.5 Improved K-best Detector and Its Performance Simulation .........................................................................................166
4.2.6 Summary and Analysis ..................................................................................................................................................172
4.3 TASER Algorithm ............................................................................................................................................... 174
4.3.1 System Model ...............................................................................................................................................................174
4.3.2 Semi-definite Relaxation ...............................................................................................................................................176
4.3.3 Algorithm Analysis ........................................................................................................................................................176
4.3.4 Performance Analysis....................................................................................................................................................179
4.3.5 Computational Complexity ...........................................................................................................................................181
CHAPTER 5 HARDWARE ARCHITECTURE FOR NONLINEAR MASSIVE MIMO DETECTION ............................................ 186
5.1 CHOSLAR hardware architecture ...................................................................................................................... 187
5.1.1 VLSI Architecture ..........................................................................................................................................................187
5.1.2 Implementation Results and Comparison .....................................................................................................................194
5.2 TASER-based hardware architecture ................................................................................................................ 197
5.2.1 Architecture Overview ..................................................................................................................................................197
5.2.2 PE ..................................................................................................................................................................................199
5.2.3 Implementation Details ................................................................................................................................................200
5.2.4 FPGA Implementation Result ........................................................................................................................................201
5.2.5 ASIC Implementation Results ........................................................................................................................................203
CHAPTER 6 DYNAMIC RECONFIGURABLE CHIPS FOR MASSIVE MIMO DETECTION .................................................... 208
6.1 Algorithm Analysis ............................................................................................................................................ 208
6.1.1 Algorithm Analysis Method ..........................................................................................................................................208
6.1.2 Common Features of Algorithms ..................................................................................................................................209
6.1.3 Computing Model .........................................................................................................................................................210
6.2 Data Path .......................................................................................................................................................... 212
6.2.1 Structure of Reconfigurable PEA .................................................................................................................................213
6.2.2 PE Structure ..................................................................................................................................................................215
6.2.3 Shared Memory ............................................................................................................................................................221
6.2.4 Interconnection .............................................................................................................................................................223
6.3 Configurition path ............................................................................................................................................ 251
6.3.1 Control Design ..............................................................................................................................................................252
6.3.2 Master Control Interface ...............................................................................................................................................252
6.3.3 Configuration Controller ...............................................................................................................................................254
6.3.4 Design of Configuration Package .................................................................................................................................256
6.3.5 Mapping Method ..........................................................................................................................................................260
CHAPTER 7 PROSPECT OF THE VLSI ARCHITECTURE FOR MASSIVE MIMO DETECTION ............................................. 269
7.1 Prospect of Server-side Applications ................................................................................................................ 269
7.1.1 Outline of 5G Communications Characteristics ............................................................................................................269
7.1.2 Outline of the Server-side Characteristics .....................................................................................................................270
7.1.3 Server-side Application .................................................................................................................................................271
7.2 Prospect of Mobile-side Application ................................................................................................................ 277
7.2.1 Application of ASIC-based Detection Chips .................................................................................................................278
7.2.2 Application of Reconfigurable Detection Chips ...........................................................................................................281
7.3 Prospect of Applications of Edge Computing ................................................................................................... 284
7.3.1 Concept of Edge Computing .........................................................................................................................................285
7.3.2 Application of Detection Chips in the Edge Computing ...............................................................................................287
Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error.After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection.
This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error.
After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.
Chapter 1 Introduction.- Chapter 2 Linear Massive MIMO Detection Algorithm.- Chapter 3 Architecture of Linear Massive MIMO Detection.- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm.- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection.- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection.- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.
Professor Leibo Liu received his bachelor's and doctoral degrees in Electronic Engineering and Microelectronics from Tsinghua University in 1999 and 2004, respectively. He subsequently taught at the European Microelectronics Center, Massachusetts Institute of Technology, and the University of Oxford (in 2006, 2013 and 2017). He is currently a Tsinghua Microelectronics Director (Tenured Professor). He has long been engaged in reconfigurable computing and has supervised more than 10 projects including key projects of the 863 Program (Chief Expert), National Natural Science Foundation, Basic Research Project of the National Defense Science and Technology Bureau, and major international cooperation projects. He has published more than 80 SCI-indexed papers and more than 60 EI-indexed papers.
In the course of his career, he has won e.g. the National Technology Invention Award (second prize), the China Patent Gold Award, the Ministry of Education Technology Invention Award (firstprize), and the Jiangxi Science and Technology Progress Award (second prize).
Über den Autor
Professor Leibo Liu received his bachelor's and doctoral degrees in Electronic Engineering and Microelectronics from Tsinghua University in 1999 and 2004, respectively. He subsequently taught at the European Microelectronics Center, Massachusetts Institute of Technology, and the University of Oxford (in 2006, 2013 and 2017). He is currently a Tsinghua Microelectronics Director (Tenured Professor). He has long been engaged in reconfigurable computing and has supervised more than 10 projects including key projects of the 863 Program (Chief Expert), National Natural Science Foundation, Basic Research Project of the National Defense Science and Technology Bureau, and major international cooperation projects. He has published more than 80 SCI-indexed papers and more than 60 EI-indexed papers.
In the course of his career, he has won e.g. the National Technology Invention Award (second prize), the China Patent Gold Award, the Ministry of Education Technology Invention Award (firstprize), and the Jiangxi Science and Technology Progress Award (second prize).
Inhaltsverzeichnis
Chapter 1 Introduction.- Chapter 2 Linear Massive MIMO Detection Algorithm.- Chapter 3 Architecture of Linear Massive MIMO Detection.- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm.- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection.- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection.- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.
Klappentext
This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error.
After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.
Present a dynamic and reconfigurable architecture for future wireless communication systems, e.g. 5G and beyond
Introduces massive multiple-input multiple-output (MIMO) technology, which can improve network capacity, enhance network robustness and reduce communication delays
Reviews various implementations of the architecture and explains the ASIC-based approach, which offers high energy efficiency, high area efficiency and low detection error
