Strategies for design-oriented ESD protection
Distributed ESD protection networks optimized for sub-90nm CMOS ICs
ESD protection strategies for smart power ICs used in automotive industry
The impact of burn-in testing (accelerated test methods) on the ESD robustness
The charge board ESD (CBM) testing used for wireless products
Manoj Sachdev has (co)authored several books for Springer/Kluwer
ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths.
Dedication. Preface. Acknowledgments. 1. INTRODUCTION. 1. Nature of ESD phenOmena. 2. ESD failures in nanometric technologies. 3. Circuit reliability: ESD models. 4. ESD challenges for advanced CMOS technologies. 5. ESD design window. 6. Book objective and organization. 7. Summary. 2. ESD MODELS AND TEST METHODS. 1. Introduction. 2. ESD zapping modes. 3. HBM model. 4. MM model. 5. CDM model. 6. CBM model. 7. TLP testing. 8. Correlation of ESD test methods. 9. ESD testers. 10. Summary. 3. ESD DEVICES FOR INPUT/OUTPUT PROTECTION. 1. Introduction. 2. Non-snapback devices. 3. Snapback devices. 4. Latch-up in ESD protection devices. 5. ESD devices under stress conditions: Burn in. 6. Failure criteria of ESD devices. 7. Summary. 4. CIRCUIT DESIGN CONCEPTS FOR ESD PROTECTION. 1. Introduction. 2. ESD protection networks. 3. Distributed ESD protection networks. 4. Circuit design flow for ESD. 5. Summary. 5. ESD POWER CLAMPS. 1. Introduction. 2. Static ESD clamp. 3. Transient power clamps. 4. Summary. 6. ESD PROTECTION CIRCUITS FOR HIGH-SPEED I/OS. 1. Introduction. 2. Parasitic capacitance of ESD protection circuits. 3. A 12-bit 20Ms/s analog to digital converter [3]. 4. A 14-bit 125Ms/s analog to digital converter [5]. 5. A 4Gb/s current mode logic driver [9]. 6. Summary. 7. ESD PROTECTION FOR SMART POWER APPLICATIONS. 1. Introduction. 2. LDMOS-based ESD protection. 3. BJT-based ESD protection. 4. SCR-based ESD protection. 5. Power bus ESD protection circuits for high voltage applications. 6. summary. 8. ESD PROTECTION FOR RF CIRCUITS. 1. Introduction. 2. Basic concepts. 3. Low noise amplifer. 4. ESD protection methods for RF circuits. 5. Summary. 9. CONCLUSION. 1. Introduction. 2. Future work. Index.
The challenges associated with the design and implementation of Electrostatic Discharge (ESD) protection circuits are becoming increasingly complex as technology is scaled well into nano-metric regime. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions. There are several challenges that must be met in order to design robust ESD circuits today. Due to technology scaling and proliferation of automated handling, ESD failures in ICs caused by Charged Device Model (CDM) are increasing. CDM discharges can cause latent damages which could degrade and eventually lead to definite failures in the ICs. The ESD protection design for current and future sub-65nm CMOS circuits is a challenge for high I/O count, multiple power domains and flip-chip products.
ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results demonstrates its strengths.
This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device and circuit simulators is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance.
ESD Models and Test Methods.- ESD Devices for Input/Output Protection.- Circuit Design Concepts for ESD Protection.- ESD Power Clamps.- ESD Protection Circuits for High-Speed I/OS.- ESD Protection for Smart Power Applications.- ESD Protection for RF Circuits.- Conclusion.
Über den Autor
Manoj Sachdev has (co)authored several books for Springer/Kluwer
Inhaltsverzeichnis
ESD Models and Test Methods.- ESD Devices for Input/Output Protection.- Circuit Design Concepts for ESD Protection.- ESD Power Clamps.- ESD Protection Circuits for High-Speed I/OS.- ESD Protection for Smart Power Applications.- ESD Protection for RF Circuits.- Conclusion.
Klappentext
The challenges associated with the design and implementation of Electrostatic Discharge (ESD) protection circuits are becoming increasingly complex as technology is scaled well into nano-metric regime. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions. There are several challenges that must be met in order to design robust ESD circuits today. Due to technology scaling and proliferation of automated handling, ESD failures in ICs caused by Charged Device Model (CDM) are increasing. CDM discharges can cause latent damages which could degrade and eventually lead to definite failures in the ICs. The ESD protection design for current and future sub-65nm CMOS circuits is a challenge for high I/O count, multiple power domains and flip-chip products.
ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results demonstrates its strengths.
Strategies for design-oriented ESD protection
Distributed ESD protection networks optimized for sub-90nm CMOS ICs
ESD protection strategies for smart power ICs used in automotive industry
The impact of burn-in testing (accelerated test methods) on the ESD robustness
The charge board ESD (CBM) testing used for wireless products
