Part I: C/C++ Based System Design 1: How Different are Esterel and SystemC? By Jens Brandt and Klaus Schneider. 2: Timed Asynchronous Circuits Modeling and Validation using SystemC by Cédric Koch-Hofer and Marc Renaudin. 3: On Construction of Cycle Approximate Bus TLMs by Martin Radetzki and Rauf Salimi Khaligh. 4: Combinatorial Dependencies in Transaction Level Models by Robert Guenzel, Wolfgang Klingauf and James Aldis. 5: An Integrated SystemC Debugging Environment by Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke. 6: Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques by Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler. 7: SystemC-based Simulation of the MICAS Architecture by Dragos Truscan, Kim Sandström, Johan Lilius, and Ivan Porres. Part II: Analog, Mixed-Signal, and Heterogeneous System Design 8: Heterogeneous Specification with HetSC and SystemC-AMS: Widening the support of MoCs in SystemC by F. Herrera and E. Villar. 9: An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations by Leran Wang, Chenxu Zhao and Tom J. Kazmierski. 10: Mixed-Level Modeling Using Configurable MOS Transistor Models by Jürgen Weber, Andreas Lemke, Andreas Lehmler, Mario Anton, Sorin A. Huss. Part III: UML-Based System Specification and Design 11: Modeling AADL data communications with UML MARTE by Charles André, Frédéric Mallet, Robert de Simone. 12: Software Real-Time Resource Modeling by Frédéric Thomas, Sébastien Gérard, Jérôme Delatour and François Terrier. 13: Model Transformations from a Data Parallel Formalism towards Synchronous Languages by Huafeng Yu and Abdoulaye Gamatié and Eric Rutten and Jean-Luc Dekeyser. 14: UML and SystemC- a Comparison and Mapping Rules for AutomaticCode Generation by Per Andersson and Martin Höst. 15: An Enhanced SystemC UML Profile for Modeling at Transaction-Level by S. Bocchio, E. Riccobene, A. Rosti, P. Scandurra. 16: SC2 StateCharts to SystemC: Automatic Executable Models Generation by Marcello Mura, Marco Paolieri. Part IV: Formalisms for Property-Driven Design. 17: Asynchronous on-line monitoring of logical and temporal assertions by K. Morin-Allory, L. Fesquet, B. Roustan, and D. Borrione. 18: Transactor-based Formal Verification of Real-time Embedded Systems by D. Karlsson, P. Eles, Z. Peng. 19: A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set by Martin Schickel, Martin Oberkönig, Martin Schweikert, and Hans Eveking.
Unique collection of selected papers from FDL'07
Improved version of papers from FDL'07
Latest research results in C/C++ Based System Design
Latest research results in Analog, Mixed-Signal, and Heterogeneous System Design
Latest research results in UML-Based System Specification and Design
Latest research results in Formalisms for Property-Driven Design