Preface nAcknowledgementsnn1: Introduction n1.1. The Deep Sub-Micron IC Designn1.2. Outlinenn2: Preliminariesn2.1. Overviewn2.2. CMOS Technologyn2.2.1. Transistorsn2.2.2. Gatesn2.2.3. CMOS storage componentsn2.2.4. Interconnectionsn2.3. IC Design and System-On-a-Chipn2.3.1. System and constraintsn2.3.2. Design stylesn2.3.3. System-On-a-Chipn2.4. Design Automationn2.5. Challenges in the Deep Sub-Micron Eran2.5.1. The Deep Sub-Micron challengesn2.5.2. Dealing with the DSM challengesn2.6. Summarynn3: Circuit Structuresn3.1.Overviewn3.2. Standard-celln3.2.1. The structure and usage of the standard-celln3.2.2. Existing design methodology for the standard-cell n3.2.3. An Integrated Standard-cell Physical Designn3.2.4. Summary of the standard-cell structuren3.3. PLA n3.4. Network of PLAsn3.5. River PLAn3.5.1. Overviewn3.5.2. The structure of the RPLAn3.5.3. The design methodologyn3.5.4. Experimental resultsn3.5.5. Summaryn3.6. Whirlpool PLAn3.6.1. The circuit structure of the WPLAn3.6.2. Doppio-ESPRESSOn3.6.3. Experimental resultsn3.6.4. Summaryn3.7. Checkerboardn3.7.1. The structure of Checkerboard and its dynamic operation n3.7.2. The algorithmn3.7.3. Experimental resultsn3.7.4. Summary and discussionn3.8. Comparison of the Structuresnn4: Block Level Placement and Routing n4.1. Overview n4.2. The Fishbone Schemen4.2.1. An overview of the Fishbone scheme n4.2.2. The basics of the Fishbone routingn4.2.3. Interval packing for branches and trunksn4.2.4. I/O-pins n4.2.5. The Fishbone placement and routing flown4.2.6. Experimental resultsn4.2.7. Summary of the Fishbone schemen4.3. Fishbone with Buffer Insertionn4.3.1. The buffers n4.3.2. Buffer insertionn4.3.3. The Fishbone-B physical design flown4.3.4. Experimental resultsn4.3.5. Summary of the Fishbone-Bn4.4. Summarynn5: The Design Flow n5.1. Overviewn5.2. Basics of the Design Flown5.2.1. Modules and pathsn5.2.2. Timing constraints for the modulesn5.2.3. The relation of module area and constraintn5.2.4. The problems and possible solutionsn5.3. The Physical Synthesis Flow n5.4. The Module Based Design Flown5.4.1. Overviewn5.4.2. The version of soft modulen5.4.3. The physical design stage n5.4.4. Summary of the Module-Based design flown5.5. Comparison of the Two Flowsn5.5. Generation of the testing examplesn5.5.2. The 0.18-micron technologyn5.5.3 The testing circuitsn5.5.4. The comparisonn5.5.5. Case study: A l n5.6. Summary nn6: ConclusionnBibliography nIndex
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy. The co-design of structures and algorithms allows great opportunities for achieving better final results, thus closing the gap between IC and CAD designers. The regularities also provide simpler and possibly better manufacturability.
In this book we present not only algorithms for solving particular sub-problems but also systematic ways of organizing different algorithms in a flow to solve the design problem as a whole. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time.