Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.
The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.
|
Power Aware Design Methodologies is on power-awareness in design. The difference between low-power design and power-awareness in design is that whereas low-power design refers to minimizing power with or without a performance constraint, power-aware design refers to maximizing some other performance metric, subject to a power budget (even while reducing power dissipation).
Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.
The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful to the circuit and system designers, tool developers, and academic researchers and students.
Power Aware Design Methodologies is written for the design professional and can be used as a textbook for an advanced course on power-aware design methodologies.
Contributors. Preface. 1. Introduction; M. Pedram, J. Rabaey. 2. CMOS Device Technology Trends for Power-Constrained Applications; D.J. Frank. 3. Low Power Memory Design; Y. Oowaki, T. Tanzawa. 4. Low-Power Digital Circuit Design; T. Kuroda. 5. Low Voltage Analog Design; K. Uyttenhove, M. Steyaert. 6. Low Power Flip-Flop and Clock Networks Design Methodologies in High-Performance System-On-A-Chip; C. Kim, S.-M.S. Kang 7. Power Optimization by Datapath Width Adjustment; H. Yasuura, H. Tomiyama. 8. Energy-Efficient Design of High-Speed Links; G.-Y. Wei, et al. 9. System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing; D. Marculescu, R. Marculescu. 10. Tools and Techniques for Integrated Hardware-Software Energy Optimizations; N. Vijaykrishnan, et al. 11. Power-Aware Communication Systems; M. Srivastava. 12. Power-Aware Wireless Microsensor Networks; R. Min, et al. 13. Circuit and System Level Power Management; F. Fallah, M. Pedram. 14. Tools and Methodologies for Power Sensitive Design; J. Frenkil. 15. Reconfigurable Processors - The Road to Flexible Power-Aware Computing; J. Rabaey, et al. Index.
CMOS Device Technology Trends for Power-Constrained Applications.- Low Power Memory Design.- Low-Power Digital Circuit Design.- Low Voltage Analog Design.- Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip.- Power Optimization by Datapath Width Adjustment.- Energy-Efficient Design of High-Speed Links.- System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing.- Tools and Techniques for Integrated Hardware-Software Energy Optimizations.- Power-Aware Communication Systems.- Power-Aware Wireless Microsensor Networks.- Circuit and System Level Power Management.- Tools and Methodologies for Power Sensitive Design.- Reconfigurable Processors - The Road to Flexible Power-Aware Computing.- Energy-Efficient System-Level Design.
Inhaltsverzeichnis
Contributors. Preface. n1. Introduction; M. Pedram, J. Rabaey. n2. CMOS Device Technology Trends for Power-Constrained Applications; D.J. Frank. n3. Low Power Memory Design; Y. Oowaki, T. Tanzawa. n4. Low-Power Digital Circuit Design; T. Kuroda. n5. Low Voltage Analog Design; K. Uyttenhove, M. Steyaert. n6. Low Power Flip-Flop and Clock Networks Design Methodologies in High-Performance System-On-A-Chip; C. Kim, S.-M.S. Kang n7. Power Optimization by Datapath Width Adjustment; H. Yasuura, H. Tomiyama. n8. Energy-Efficient Design of High-Speed Links; G.-Y. Wei, et al. n9. System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing; D. Marculescu, R. Marculescu. n10. Tools and Techniques for Integrated Hardware-Software Energy Optimizations; N. Vijaykrishnan, et al. n11. Power-Aware Communication Systems; M. Srivastava. n12. Power-Aware Wireless Microsensor Networks; R. Min, et al. n13. Circuit and System Level Power Management; F. Fallah, M. Pedram. n14. Tools and Methodologies for Power Sensitive Design; J. Frenkil. n15. Reconfigurable Processors - The Road to Flexible Power-Aware Computing; J. Rabaey, et al. nIndex.
Klappentext
Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.
The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.
