HIGH-K TECHNOLOGY. PVD-High-k Gate Dielectrics with FUSI Gate and Influence of PDA Treatment on On-state Drive Current; M. Niwa et al.- Extremely High Density Capacitors with ALD High-k Dielectric Layers; J. Klootwijk et al.- Towards Understanding of Processing-nanostructure-property Inter-relationships in High-k/Metal Gate Stacks; P.Majhi et al.- DEFECTS IN HIGH-K DIELECTRICS: CHARACTERIZATION. On the Characterization of Electronically Active Defects in High-k Gate Dielectrics; D.A. Buchanan and D. Felnhofer.- Inelastic Electron Tunnelling Spectroscopy (IETS) Study of High-k Dielectrics; T.P. Ma et al.- Characterization and Modeling of Defects in High-k Layers Through Fast Electrical Transient Measurements; J. Mitard et al.- Characterization of Electrically Active Defects in High-k Gate Dielectrics Using Charge Pumping; E. M. Vogel and D. W. Heh.- Impact of High-k Properties on MOSFET Electrical Characteristics; L. Pantisano et al.- HIGH-K PROCESSING AND DEFECTS. Structural Evolution and Point Defects in Metal Oxide-based High-k Gate Dielectrics; P. C. McIntyre et al.- Disordered Structure and Density of Gap States in High-Permittivity Thin Solid Films; K. Kukli et al.- Interdiffusion Studies of High-k Gate Dielectric Stack Constituents; P. Sivasubramiani et al.- XPS/LEIS Study of High-k Rare Earth (Lu, Yb) Oxides and Silicates on Si: The Effect of Annealing on Microstructure Evolution; A.Zenkevich et al.- Transient Charging Effects and Its Implications to The Reliability of High-k Dielectrics; B. H. Lee et al.- HIGH-K HEORY. Defect Energy Levels in High-k Gate Oxides; J. Robertson et al.- Defect-related Issues in High-k Dielectrics; S. T. Pantelides et al.- Studying The Effects of Nitrogen and Hafnium Incorporation into The SiO2/Si(100) Interface with Replica-exchange Molecular Dynamics and Density-Functional-Theory Calculations; W. Androni et al.- ELECTRICALLY ACTIVE DEFECTS. Probing Point Defects and Traps in Stacks of Ultrathin Hafnium Oxides on (100)Si by Electron Spin Resonance: Interfaces and N Incorporation; A. Stesmans and V. V. Afanas'ev.- Mechanism of Charge Trapping Reduction in Scaled High-k Gate Stacks; G. Bersuker et al.- Electrically Active Interface and Bulk Semiconductor Defects in High-k / Germanium Structures; A. Dimoulas.- Defect and Composition Analysis of As-deposited and Nitrided (100)Si / SiO2/ Hf1-xSixO2 Stacks by Electron Paramagnetic Resonance and Ion Beam Analysis; H. J. von Bardeleben et al.- Defects at The High-k /Semiconductor Interfaces Investigated By Spin Dependent Spectroscopies; M. Fanciulli et al.- Fixed Oxide Charge in Ru-based Chemical Vapour Deposited High-k Gate Stacks; K. Frohlich et al.- Electrical Defects in Atomic Layer Deposited HfO2 Films on Silicon: Influence of Precursor Chemistries and Substrate Treatment; S. Dueñas et al.- The Effects of Radiation and Charge Trapping on The Reliability of Alternative Gate Dielectrics; J. A. Felix et al.- Can LEIS Spectra Contain Information on Surface Electronic Structure of High-k Dielectrics; Yu. Lebedinskii et al.- Low Substrate Damage High-k Removal After Gate Patterning; D. Shamiryan et al.- Monitoring of Fermi Level Variations at Metal/High-k Interfaces with in situ X-ray Photoelectron Spectroscopy; Yu. Lebedinskii et al.- INTERFACES. Structure, Composition and Order at Interfaces of Crystalline Oxides and Other High-k Materials on Silicon; T. Gustafsson et al.- Interface Formation During Epitaxial Growth of Binary Metal Oxides on Silicon; H. J. Osten et al.- Chemical Environment and Strain on Oxygen Vacancy Formation Energies at Silicon-Silicon Oxide Interfaces; T.M. Henderson.- Dielectric and Infrared Properties of Ultrathin SiO2 Layers on Si (100); F. Giustino and A. Pasquarello.- The (1 0 0) Surface of Semiconductor Silicon (in Practical Conditions). Preparation, Evolution, Passivation;
The goal of this NATO Advanced Research Workshop (ARW) entitled "Defects in Advanced High-k Dielectric Nano-electronic Semiconductor Devices", which was held in St. Petersburg, Russia, from July 11 to 14, 2005, was to examine the very complex scientific issues that pertain to the use of advanced high dielectric constant (high-k) materials in next generation semiconductor devices. The special feature of this workshop was focus on an important issue of defects in this novel class of materials. One of the key obstacles to high-k integration into Si nano-technology are the electronic defects in high-k materials. It has been established that defects do exist in high-k dielectrics and they play an important role in device operation. However, very little is known about the nature of the defects or about possible techniques to eliminate, or at least minimize them. Given the absence of a feasible alternative in the near future, well-focused scientific research and aggressive development programs on high-k gate dielectrics and related devices must continue for semiconductor electronics to remain a competitive income producing force in the global market.
To the best of our knowledge, this is the first focused collection of papers on DEFECTS in high-k dielectrics materials
State-of-the-art reviews from leading experts in the field of high-k dielectrics
Covered from different angles, including silicon technology, processing aspects, materials properties, electrical defects, microstructural studies, and theory