Autor/Autorin: Asati Abhijit
Dr. Abhijit Asati completed Ph.D. degree (in 2010) and M.E. degree (in 2002) from BITS Pilani. Prior to this, he completed B.E. degree in electrical engineering from Amravati University in the year 1996. He has more than 15 years of experience in academia and currently working as 'Assistant Professor' in the EEE department at BITS Pilani.
The objective of this book is to explore the design space of two specific data path elements (viz multipliers and barrel shifters) of different bit width at architectural-level, at logic design level, and at transistor size level to select proper architecture, logic design style and physical device sizes; keeping in a view their effects on performance (circuit delay), average power consumption and core area. The multipliers and barrel shifters are the fundamental data path elements required in high performance `Standard Digital Signal Processors´ and `ASIC Digital Signal Processors´ used for digital signal processing (DSP). Different multiplier and barrel shifter architectures show trade-offs between propagation delay, average power consumption and transistor counts. In deep sub-micron technologies, the simple gate-level analyses are inadequate to validate particular data path architectures. In this work we considered the effects of wiring parasitics and MOS parasitics in the assessment of architecture. The selected word widths for different multiplier and barrel shifter architectures are 4-bit, 8-bit, 12-bit and 16-bit; which dominate in DSP applications.
The objective of this book is to explore the design space of two specific data path elements (viz multipliers and barrel shifters) of different bit width at architectural-level, at logic design level, and at transistor size level to select proper architecture, logic design style and physical device sizes; keeping in a view their effects on performance (circuit delay), average power consumption and core area. The multipliers and barrel shifters are the fundamental data path elements required in high performance 'Standard Digital Signal Processors' and 'ASIC Digital Signal Processors' used for digital signal processing (DSP). Different multiplier and barrel shifter architectures show trade-offs between propagation delay, average power consumption and transistor counts. In deep sub-micron technologies, the simple gate-level analyses are inadequate to validate particular data path architectures. In this work we considered the effects of wiring parasitics and MOS parasitics in the assessment of architecture. The selected word widths for different multiplier and barrel shifter architectures are 4-bit, 8-bit, 12-bit and 16-bit; which dominate in DSP applications.
Dr. Abhijit Asati completed Ph.D. degree (in 2010) and M.E. degree (in 2002) from BITS Pilani. Prior to this, he completed B.E. degree in electrical engineering from Amravati University in the year 1996. He has more than 15 years of experience in academia and currently working as 'Assistant Professor' in the EEE department at BITS Pilani.
Über den Autor
Dr. Abhijit Asati completed Ph.D. degree (in 2010) and M.E. degree (in 2002) from BITS Pilani. Prior to this, he completed B.E. degree in electrical engineering from Amravati University in the year 1996. He has more than 15 years of experience in academia and currently working as 'Assistant Professor' in the EEE department at BITS Pilani.
Klappentext
The objective of this book is to explore the design space of two specific data path elements (viz multipliers and barrel shifters) of different bit width at architectural-level, at logic design level, and at transistor size level to select proper architecture, logic design style and physical device sizes; keeping in a view their effects on performance (circuit delay), average power consumption and core area. The multipliers and barrel shifters are the fundamental data path elements required in high performance ¿Standard Digital Signal Processors¿ and ¿ASIC Digital Signal Processors¿ used for digital signal processing (DSP). Different multiplier and barrel shifter architectures show trade-offs between propagation delay, average power consumption and transistor counts. In deep sub-micron technologies, the simple gate-level analyses are inadequate to validate particular data path architectures. In this work we considered the effects of wiring parasitics and MOS parasitics in the assessment of architecture. The selected word widths for different multiplier and barrel shifter architectures are 4-bit, 8-bit, 12-bit and 16-bit; which dominate in DSP applications.
