Dedicated verification techniques for the different abstraction levels of System C
Verification quality is measured throughout the refinement of the design
Integrated design and verification flow
Dedication. List of Figures. List of Tables. Preface. Acknowledgments. 1. INTRODUCTION. 2. PRELIMINARIES. 2.1 Boolean Reasoning. 2.2 Circuits. 2.3 Formal Verification. 2.4 SystemC. 3. SYSTEM-LEVEL VERIFICATION. 3.1 Constraint-based Simulation. 3.2 Improvements for Constraint-based Simulation. 3.3 Contradiction Analysis for Constraint-based Simulation. 3.4 Measuring the Quality of Testbenches. 3.5 Summary and Future Work. 4. BLOCK-LEVEL VERIFICATION. 4.1 Property Checking. 4.2 Acceleration of Iterative Property Checking. 4.3 Contradictory Antecedent Debugging for Property Checking. 4.4 Analyzing Functional Coverage in Property Checking. 4.5 Summary and Future Work. 5. TOP-LEVEL VERIFICATION. 5.1 Checker Generation. 5.2 HW/SW Co-Verification for Embedded Systems. 5.3 Summary and Future Work. 6. SUMMARY AND CONCLUSIONS. References. Index.
Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system deillegalscription language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable deillegalscriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly.
Therefore a quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.
This text offers a quality-driven design and verification flow for digital systems. Dedicated verification techniques are integrated which target the different levels of abstraction, and each technique has a means to measure the achieved verification quality.
A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.
Preliminaries.- System-Level Verification.- Block-Level Verification.- Top-Level Verification.- Summary and Conclusions.
Inhaltsverzeichnis
Dedication. List of Figures. List of Tables. Preface. Acknowledgments. 1. INTRODUCTION. 2. PRELIMINARIES. 2.1 Boolean Reasoning. 2.2 Circuits. 2.3 Formal Verification. 2.4 SystemC. 3. SYSTEM-LEVEL VERIFICATION. 3.1 Constraint-based Simulation. 3.2 Improvements for Constraint-based Simulation. 3.3 Contradiction Analysis for Constraint-based Simulation. 3.4 Measuring the Quality of Testbenches. 3.5 Summary and Future Work. 4. BLOCK-LEVEL VERIFICATION. 4.1 Property Checking. 4.2 Acceleration of Iterative Property Checking. 4.3 Contradictory Antecedent Debugging for Property Checking. 4.4 Analyzing Functional Coverage in Property Checking. 4.5 Summary and Future Work. 5. TOP-LEVEL VERIFICATION. 5.1 Checker Generation. 5.2 HW/SW Co-Verification for Embedded Systems. 5.3 Summary and Future Work. 6. SUMMARY AND CONCLUSIONS. References. Index.
Klappentext
A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.
Dedicated verification techniques for the different abstraction levels of System C
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Verification quality is measured throughout the refinement of the design
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Integrated design and verification flow
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