Variation Tolerant On-Chip Interconnects

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

Predictive Technology Model for Robust Nanoelectronic Design

Ultra-Low Power Integrated Circuit Design

An ASIC Low Power Primer

Variation Tolerant On-Chip Interconnects

The Art of Hardware Architecture

Synthesis of Computational Structures for Analog Signal Processing

Embedded Systems Design with FPGAs

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Power-efficient System Design

Minimizing and Exploiting Leakage in VLSI Design

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

Analog Circuit Design

Low Power Networks-on-Chip

The Art of Hardware Architecture

Synthesis of Computational Structures for Analog Signal Processing

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Pipelined ADC Design and Enhancement Techniques

Ultra-Low Energy Domain-Specific Instruction-Set Processors

Analog Circuit Design

Digital Logic Design Using Verilog

An ASIC Low Power Primer

Embedded Systems Design with FPGAs

ASIC Design and Synthesis

Digital Logic Design Using Verilog

Digital Design from the VLSI Perspective

Low-Power Design and Power-Aware Verification

Low-Power Design and Power-Aware Verification

Digital Logic Design Using Verilog

ASIC Design and Synthesis

Digital Logic Design Using Verilog