Fehlertolerante Latches und Flip-Flops mit geringem Stromverbrauch

Latches e Flip-flop a bassa potenza con tolleranza ai guasti

Travas e Flip-flops tolerantes a falhas de energia baixas

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Latches y Flip-flops de bajo consumo y tolerantes a fallos

Sauts et bascules tolérants aux fautes et à faible puissance

Flip-Flop Design in Nanometer CMOS

Circuitos digitales y elementos arquitectónicos

GDI: Power & Area Efficient Digital Circuits for Portable Devices

Digital Circuits - for the digitally controlled devices

Digital circuits and architecture elements

Digitale Schaltkreise und Architekturelemente

Circuiti digitali ed elementi architettonici

Circuitos digitais e elementos arquitectónicos

Cifrowye shemy i arhitekturnye älementy

Wafer-Level Integrated Systems

Practical Low Power Digital VLSI Design

Energy Recovery Clocking Scheme to Achieve Ultra Low-Power

Design and Analysis of Clock Subsystem Elements

AN IMPROVED TRAFFIC LIGHTING SYSTEM

Wafer-Level Integrated Systems

Hardware Design and Simulation in VAL/VHDL

Automated Calibration of Modulated Frequency Synthesizers

Basic Digital Electronics

Nuclear Electronics

Implementazione di un flip-flop ottico in fibre drogate all'Er³

Solved Problems in Digital Logic

Low Power Fault Tolerant Latches and Flip-flops

Digital Electronics

Practical Low Power Digital VLSI Design

Englisch für Elektroniker

Automated Calibration of Modulated Frequency Synthesizers

Power Aware Design Methodologies

Closing the Gap Between ASIC & Custom

High-Speed Clock Network Design

Closing the Gap Between ASIC & Custom

Power Aware Design Methodologies

Single Event Upsets in Sub-65nm CMOS technologies

Elektronische Schaltungen 2

Self-Timed Control of Concurrent Processes

Elektronische Schaltungen 2

High-Speed Clock Network Design

Hardware Design and Simulation in VAL/VHDL

Power Aware Computing

Power Aware Computing